Hi, I am using mini2440 I know that the dm9000 Ethernet used on this board. But Why Ethernet controller is not described in TRM S3C2440, any specific reason or it's described some where? Can u please help me. Regards, ./J
I don't understand the question. If you know the Mini2440 uses a DM9000 Ethernet controller then why would you expect to find it documented in the S3C2440 manual? Regards, Rob
Sorry, I am bit unclear.. I am trying to explain a bit.. As I know from the memory map 0x48000000 to 0x60000000 is occupied by peripherals like rtc, watchdog, i2c ...etc. But I couldn't find the address map for Ethernet with in that range. I don't understand why 7 memory banks are categories, on which first 4KB is for ROM but what is the purpose of remaining memory. Can any one explain why these banks are meant for...any link/doc related to this may helpful. Thanks, ./J
The S3C2440 manual explains the on-chip peripherals. For the off-chip peripherals this CPU comes with an address/data bus and a few chip select lines. And on some boards (like the Mini2440) an ethernet controller is connected to these lines as an off-chip peripheral. So, the S3C2440 datasheet cannot tell you something about it.
Take a look to the figure 5-1 "S3C2440A Memory Map after Reset" (in my datasheet on page 194). Then take a look into the schematics and find to which chip select (nGCS*) the external network controller is connected to and then you know the address area where this device is visible to the CPU and your software.
Thanks for your info. I am able to found the link. Could you please tell me on how many are on-chip or how many are off-chip peripherals on mini2440? Will all off-chip peripherals uses uses these nGCS* banks and on-chip peripherals are start from 0x48000000 to 0x60000000? Can u explain about the usage of memory banks nGCS*? Thanks, ./J
on-chip: read the processor's manual off-chip: depends on the board. On the Mini2440 only the network controller and the NOR flash are connected to the available chip select lines. > Will all off-chip peripherals use these nGCS* banks and > on-chip peripherals are start from 0x48000000 to 0x60000000? Yes. But only if we talk about off-chip peripherals which require an adress/data bus (like the network controller do). There are also others in the wild, which are using SPI or I2C, or USB and so on. > Can u explain about the usage of memory banks nGCS*? ????
Hi Jagan. The ARM is a single address architecture with memory mapped I/O. AS you noticed, even inside the SOC, the peripherals are mapped to normal memory space. It really works the same, inside or outside the ship. I would suggest this book. ARM System-on-Chip Architecture (Check title on Amazon) By Steve Furber, one of the original creators of the ARM and inspired by the 6502. Note: The parlance of the day is "Load/Store" architecture, which sound like a 2 address operation to me. So I still use the old "one address" or "single address" monikers. Load/Store has about as much meaning as "granularity" (fineness would be the word they are looking for).